Field of the Invention
The invention relates to a method for examining structures on a wafer.
Wafers of this type are typically formed by silicon wafers and serve for fabricating integrated circuits and the like.
Integrated circuits of this type contain complex configurations of transistors, memory cells and the like which are contact-connected via interconnects which run in different planes.
In particular, photolithography processes are also used for fabricating structures of this type. In photolithography processes of this type, resist layers are applied to the wafer in predetermined planes. The resist layers are exposed in predetermined patterns by exposure systems, as a result of which these points on the resist layer are chemically altered. Afterward, the exposed or unexposed regions of the resist layer are removed. The resist patterns thus obtained form a mask for subsequent process steps, such as etching processes, for example.
What is problematic is that the exposure processes cannot be carried out with arbitrary accuracy. This results in so-called overlay errors, in other words displacements of different planes with respect to one another are produced when a plurality of successive exposure processes are carried out. Moreover, so-called registration errors are produced, which stem from the fact that a mask cannot be aligned with arbitrary accuracy relative to the wafer.
Errors of this type lead to an offset of structures between different planes. Furthermore, production and process-dictated fluctuations of the imaging can also occur during exposure processes within a plane. Fluctuations of this type are caused, in particular, by virtue of the fact that the imaging properties of the exposure system can vary over the respective image plane. Furthermore, such process-dictated fluctuations in structures within a plane can be caused by virtue of the fact that there are inhomogeneities in the resist layer. Finally, such structure fluctuations can be caused by inhomogeneities of the production processes, such as, for example, etching processes, sputtering processes, for which the above-mentioned masks are required.
Optical examination methods have proved successful in particular for examining overlay and registration errors. For this purpose, test patterns are disposed at predetermined positions of a plane and are examined by the exposure system. In this case, the test patterns can be formed by overlay targets, for example, which can be used to measure the offset between two planes. Furthermore, test patterns, which have minimal structures and may be configured in the form of periodic or isolated structures may be provided at predetermined positions. The structure sizes preferably correspond to the minimal structure size occurring in the respective process. The variation of the line widths over the individual test patterns during exposure by the exposure system enables statements to be made about the fluctuations of such structure patterns over the wafer surface.
Examination methods of this type have the disadvantage, however, that structure errors of circuit configurations, in particular including the location dependencies thereof, can only be detected incompletely by the methods.
It is accordingly an object of the invention to provide a method for examining structures on a wafer which overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which it is ensured the most accurate and comprehensive examination possible of structures on a wafer occur.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for examining structures on a wafer. The method includes applying at least one mask on the wafer and the mask is fabricated by exposure processes and is used for fabricating the structures. Test circuits are formed on the mask in predetermined reference positions, and the test circuits are formed with test transistors having test structures including gate oxide regions, source/drain regions and deep trench regions. In a location-dependent manner, electrical parameters of the test circuits are detected and evaluated for evaluating the structures and the exposure processes.
According to the invention, test circuits with test structures are placed on at least one mask applied on a wafer in predetermined reference positions.
In order to check the structures and/or the exposure processes, electrical parameters of the test circuits are evaluated in a location-dependent manner.
The basic concept of the invention thus consists in using electrical parameters of test circuits for checking structures on the wafer and/or exposure processes.
A suitable configuration of the test circuits on the wafer surface enables, through a location-dependent evaluation of the electrical parameters of the test circuits, not only the determination of overlay and registration errors but also a detailed and accurate checking of fluctuations of imaging parameters of the exposure processes used and also of inhomogeneities during production processes. In particular, it is possible to detect production fluctuations of the production processes used during the processing of the wafer, such as, for example, etching processes or sputtering processes. Furthermore, it is also possible to detect inhomogeneities in the resist layer of the respective mask. The test circuits are particularly advantageously disposed in the scribe lines of the wafer, which extend in a chessboard-like manner over the wafer surfaces. In this case, the test circuits are preferably distributed as uniformly as possible over the entire wafer surface. In this way, it is possible to detect fluctuations of the exposure processes and production processes completely over the entire wafer surface.
In a particularly advantageous embodiment of the invention, the test circuits contain test transistors, which are embedded in transistor arrays as reference environments. In this case, the test transistors have minimal structure sizes with regard to the surrounding transistor arrays and preferably also with regard to the structures on the wafer.
Inhomogeneities of the structures of the test transistors, the inhomogeneities being caused by line width fluctuations of the exposure system and also by fluctuations of the individual production processes, can be detected by a location-dependent measurement of the electrical parameters of the test transistors, in particular the threshold voltages thereof.
The location-dependent evaluation of the electrical parameters makes it possible, in particular, to make accurate statements about the variation of the structures over the wafer surface and also to derive correction values for the electrical parameters of such structures. Such correction values are particularly advantageously used for dimensioning the parameters of the structures on the wafer. Such structures, in the same way as the test circuits, may be formed by transistors, for example. The correction values specify, for example, the range within which the parameters of the transistor may vary. Accordingly, the transistors are configured in such a way that they are insensitive to the parameter fluctuations that occur.
In accordance with an added mode of the invention, there is the step of detecting variations in lengths of the gate oxide regions by measuring the electrical parameters of the test transistors, the variations being caused by line width fluctuations in the exposure processes.
In accordance with an additional mode of the invention, there is the step of detecting an offset of the source/drain regions with respect to the gate oxide regions and the deep trench regions by measuring the electrical parameters of the test transistors.
In accordance with another mode of the invention, there is the step of evaluating threshold voltages of the test transistors as the electrical parameters.
In accordance with a further mode of the invention, there is the step of determining location-dependent fluctuations of electrical parameters of the structures to be examined by measuring the electrical parameters of the test circuits.
In accordance with a further added mode of the invention, there is the step of deriving correction values from the location-dependent fluctuations of the electrical parameters of the structures. The correction values are used for dimensioning the electrical parameters of the structures on the wafer.
In accordance with another additional mode of the invention, there is the step of placing the test circuits in scribe lines of the mask.
In accordance with a concomitant mode of the invention, there is the step of distributing the test circuits in the scribe lines entirely over the wafer surface.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for examining structures on a wafer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.